
/*
 * hms_evb_h8s2633f.S - board-specific code
 *
 * Copyright (C) 2002 Magnus Damm <damm@opensource.se>
 *
 * This code is released under the terms of GPL.
 * 
 * This is the boot code that is uploaded to the h8s/2633f-cpu
 * via the ufpb-board. Most of it is pretty generic, but it is
 * designed for the evb-h8s/2633f-board that has external ram.
 * We are initializing 128Kbytes external ram (CS1) in "board_init".
 * It is in the external ram at 0x00200000 we should load the RTOS.
 * We do have 256Kbytes external ram on the evb-board, but the
 * serial port-pins and the required address-bus pins are shared,
 * so we stick with 128Kbytes for now.
 *
 * We also enable RAM Emulation to be able to use interrupts. 
 *
 * We don't use any flash at all.
 * All this because maximum 100 programming cycles are supported...
 */
	
	
#include "board.h"

#define STACK_TOP 0xffefac	
		
	SELECT_CPU
	.text

#define P1DDR  0xfe30:16
#define P1DR   0x00:8 /* same as 0xff00:16 */
#define P1DATA 0xb0:8 /* same as 0xffb0:16 */

#define P1_PIN_PMODE   0x80
#define P1_PIN_USERLED 0x20

	.global pins_init
pins_init:	
	mov.b #(P1_PIN_PMODE + P1_PIN_USERLED), r0l   /* pins are outputs */
	mov.b #P1_PIN_USERLED, r1l   
	mov.b r0l, @P1DDR
	mov.b r1l, @P1DR
	rts			

	.global pins_led_toggle	
pins_led_toggle:	
	mov.b @P1DATA, r0l
	xor.b #P1_PIN_USERLED, r0l
	mov.b r0l, @P1DR
	rts
	
	.global pins_led_off
pins_led_off:	
	mov.b @P1DATA, r0l
	or.b #P1_PIN_USERLED, r0l
	mov.b r0l, @P1DR
	rts

#define RAMER  0xfedb:16

#define ABWCR  0xfed0:16
#define ASTCR  0xfed1:16
#define WCRL   0xfed3:16
#define PFCR   0xfdeb:16
	
#define PADDR  0xfe39:16
#define PBDDR  0xfe3a:16
#define PCDDR  0xfe3b:16
#define PGDDR  0xfe3f:16

	.global board_init
board_init:

#ifdef BUILD_FOR_UFPB
	/* RAMER: enable RAM emulation for interrupt vectors */
	
	mov.b #8, r0l
	mov.b r0l, @RAMER
#endif

	/* ABWCR: CS1 should be 16-bit */

	bclr #1, @ABWCR

	/* WCRL: CS1 should have 0 waitstates */

	bclr #2, @ABWCR
	bclr #3, @ABWCR

	/* ASTCR: CS1 should be the fastest one */

	bclr #1, @ASTCR

	/* PFCR: 128k adresses */
#ifdef BUILD_FOR_UFPB
	mov.b #0x9, r0l
#endif	
#ifdef BUILD_FOR_FLASH
	mov.b #0xa, r0l /* only working when A17 is not used by SCI2 */
#endif
	mov.b r0l, @PFCR

	/* PGDDR: The CS1 pin should be configured as CS1 */

	mov.b #0x8, r0l
	mov.b r0l, @PGDDR

	/* PADDR, PBDDR, PCDDR: Configure the address-pins */

	mov.b #0xff, r0l
	mov.b r0l, @PCDDR
	mov.b r0l, @PBDDR
	mov.b #0x3, r0l
	mov.b r0l, @PADDR

	jsr	pins_init
	
	rts






